1. Field of the Invention
The present invention is in the field of clock generator circuits for digital signal processors and the like.
2. Description of the Related Art
To control the individual functional units in digital signal processing circuits, a nonoverlapping two-phase clock is frequently necessary. Such a clock comprises a first clock and a nonoverlapping second clock. These two clocks are generated in a two-phase clock generator from a unipolar input clock which usually has a 1:1 mark/space ratio. At high signal-processing speeds, the derivation of the two overlapping clocks from a higher-frequency clock by logic combination of high and low states is no longer possible. By utilizing gate delays, however, non-overlapping clocks can be generated even at high frequencies. A typical feature of these prior art circuit arrangements is that the clock signal from the respective clock output is fed back to a logic gate contained in the respective other signal path, i.e., the feedback paths are cross-connected to the respective other signal path.
Through this signal feedback, one of the two logic gates does not change its state until the output signal in the other signal path has assumed a new state. In this manner, nonoverlapping is ensured. The nonoverlap period is determined at least by the delays of the gates in the respective signal path, which, as a rule, comprises the logic gate, several inverter stages, and an output buffer. The second inputs of the logic gates are fed with an antiphase signal derived from the input clock by means of additional inverter stages.
One disadvantage of such two-phase clock generators is that at high clock frequencies, the nonoverlap period is relatively long, so that the active clock phase is unnecessarily limited in time. On the other hand, the number of gates cannot be reduced indefinitely since in the NOR or NAND gates used, the phase of the clock fed back must be taken into consideration, so that the minimum number of gates, usually inverters, is predetermined.